Digital Design - Autumn 2019

Course Information:

Outline

Course Syllabus

Publisher's Web Site

School of Engineering Homework Standards

D2L

Project:

• Project Description
• Project Assignment #1 - Instruction Set Design, Due Wed, 11/13
  • Examples of Booth's Multiplication Algorithm

Lecture:

• Combinational Circuit Review
• Sequential Circuit Review
• Implementation and Simulation
• Registers and Counters
• Chapter 1 - Introduction to Digital System Design
• Chapter 2 - Overview of Hardware Description Languages
• Chapter 3 - Basic Language Constructs of VHDL
• Chapter 4 - Concurrent Signal Assignment Statements of VHDL
• Chapter 5 - Sequential Statements of VHDL
• Chapter 8 - Sequential Circuit Design: Principle
• VHDL Examples
• VHDL Style Observations

Homework:

• #1 - Combinational Circuit Review, Due Fri, 9/27
• #2 - Sequential Circuit Review - Part I, Due Wed, 10/2
• #3 - Sequential Circuit Review - Part II, Due Fri, 10/4
• #4 - Sequential Circuit Review - Part III, Due Mon, 10/7
• #5 - Sequential Circuit Review - Part IV, Due Tues, 10/8, 2pm
• #6 - Digital Systems Design, Due Tues, 10/22, 2pm
• #7 - Chapter 2, Hardware Description Languages, Due Fri, 10/25, 2pm
• #8 - Chapter 3, Basic VHDL Language Constructs, Due Wed, 10/30
• #9 - Chapter 4, Concurrent Signal Assignments, Due Mon, 11/4
• #10 - State Machine Design, Due Fri, 11/8, 2pm

Lab:

Lab1 - Digital Noise, Voltage Sources, and Capacitor Performance

• Lab Handout

Lab2 - State Machine Design and Implementation with MSI Circuits

• Lab Handout

Lab3 - Schematic Entry Using Xilinx Tools - Basic

• Lab Handout

Lab4 - Schematic Entry Using Xilinx Tool - Advanced

• Lab Handout

Lab5 - Combinational Circuit Implementation in VHDL

• Lab Handout

Lab6 - State Machine Implementation in VHDL

• Lab Handout
  • Clock Code (.vhd)
  • States Example (.vhd)

Lab Support:

FPGA Boards

• Constraints file for WWU fpga3 board, individual names version, commented out (text)
• Constraints file for WWU fpga3 board, vector version, commented out (text)
• WWU FPGA3 Board Schematic (pdf)
• Binary to 7-Segment Decoder Table (pdf)

Xilinx Spartan-6 FPGA Data:

• Overview (pdf)
• Data Sheet (pdf)
• Schematic Library Reference Manual (pdf)
• Configurable Logic Blocks (pdf)
• Configuration Users Guide (pdf)
• Packages and Pinouts (pdf)

Xilinx 14.7 ISE Manuals:

• VHDL Library Reference Guide (pdf)
• Synthesis and Simulation Design Guide (pdf)
• Constraints Guide (pdf)
• VHDL Entry Using ISE 14.7 (pdf)
• Schematic Entry Using ISE 14.7 (pdf)
• Adding a Bus Tap (web page)

Datasheets:

• Short Version of All Data Sheets
• 74HC00 (Quad 2-Input NAND Gates)
• 74HC02 (Quad 2-Input NOR Gates)
• 74HC04 (Hex Inverter Gates)
• 74HC10 (Triple 3-input NAND Gates)
• 74HC20 (Dual 4-input NAND Gates)
• 74HC27 (Triple 3-input NOR Gates)
• 74HC74 (Dual Positive Edge-Triggered D Flip-Flops)
• 74HC86 (Quad 2-Input XOR Gates)
• 74HC138 (3-to-8 Decoder/Demultiplexer)
• 74HC139 (Dual 2-to-4 Decoder/Demultiplexer)
• 74HC151 (8-to-1 Multiplexer)
• 74HC153 (Dual 4-to-1 Multiplexer)
• 74HC163 (4-bit Synchronous Binary Counter)

Tests:

• Exam #1 Review Sheet

Simulators:

• Logisim Logic Simulator
• Falstad Logic Simulator